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CMOS Highly Accurate : 2% Low Power Consumption : 0.7 A (VIN = 1.5V) Ultra Small Package : USP-3
APPLICATIONS
Microprocessor reset circuitry Memory battery back-up circuits Power-on reset circuits Power failure detection System battery life and charge voltage monitors
GENERAL DESCRIPTION
The XC61G series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. Detect voltage is extremely accurate with minimal temperature drift. Both CMOS and N-channel open drain output configurations are available.
FEATURES
Highly Accurate : 2% Low Power Consumption : 0.7 A [ VIN=1.5V ] (TYP.) Detect Voltage Range : 0.8V ~ 1.5V in 100mV increments(Low Voltage) : 1.6V 6.0V in 100mV increments(Standard Voltage) Operating Voltage Range : 0.7V ~ 6.0V(Low Voltage) : 0.7V 10.0V(Standard Voltage) Detect Voltage Temperature characteristics : 100ppm/ (TYP.) Output Configuration : N-channel open drain or CMOS Ultra Small Package : USP-3(120mW)
TYPICAL APPLICATION CIRCUITS
TYPICAL PERFORMANCE CHARACTERISTICS
101
XC61G Series
PIN CONFIGURATION PIN ASSIGNMENT
PIN NUMBER USP-3 3 1 2 PIN NAME VIN VSS VOUT FUNCTION Supply Voltage Ground Output
PRODUCT CLASSIFICATION
Ordering Information XC61G
DESIGNATOR DESCRIPTION Output Configuration SYMBOL C N 08 ~ 60 0 2 H R L DESCRIPTION : CMOS output : N-ch open drain output : e.g. 0.9V : e.g. 1.5V : No delay : Within : USP-3 : Embossed tape, Standard feed : Embossed tape, Reverse feed 2% 0, 1, 9 5
Detect Voltage Output Delay Detect Accuracy Package Device Orientation
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XC61G
Series
PACKAGING INFORMATION
USP-3
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XC61G Series
MARKING RULE
USP-3
USP-3 TOP VIEW
Represents integer of output voltage and detect voltage CMOS Output (XC61GC series) MARK CONFIGURATION A CMOS B CMOS VOLTAGE(V) 0.X 1.X N-Channel Open Drain Output (XC61GN series) DESIGNATOR CONFIGURATION VOLTAGE(V) K N-ch 0.X L N-ch 1.X
Represents decimal number of detect voltage MARK 0 1 2 3 4 VOLTAGE (V) DESIGNATOR X.0 5 X.1 6 X.2 7 X.3 8 X.4 9 VOLTAGE (V) X.5 X.6 X.7 X.8 X.9
Based on internal standards ( SSOT-24 excepted ) MARK 3 Represents production lot number 0 to 9, A to Z repeated (G,I,J,O,Q,W excepted)
BLOCK DIAGRAMS
(1)CMOS Output (2)N-ch Open Drain Output
104
XC61G
Series
ABSOLUTE MAXIMUM RATINGS
Ta = 25 PARAMETER Input Voltage Output Current Output Voltage *1 *2 *1 *2 SYMBOL VIN IOUT VOUT Pd Topr Tstg RATINGS 9.0 12.0 50 50 VSS -0.3 ~ VIN +0.3 VSS -0.3 ~ 9.0 VSS -0.3 ~ 12.0 120 -40 +85 -40 +125 UNITS V mA V mW
CMOS N-ch Open Drain Output *1 N-ch Open Drain Output *2
Power USP-3 Dissipation Operating Temperature Range Strage Temperature Range
*1 Low voltage *2 Standard voltage
ELECTRICAL CHARACTERISTICS
VDF (T) = 0.9 to 1.5V 2% Ta=25
PARAMETER Detect Voltage Hysteresis Range
SYMBOL VDF VHYS
Supply Current
ISS
Operating Voltage Output Current (Low Voltage)
VIN
MIN. VDF x 0.98 VDF x 0.02 VIN = 1.5V = 2.0V = 3.0V = 4.0V = 5.0V VDF(T) = 0.9V to 1.5V 0.7 0.7 VDF(T) = 1.6V to 6.0V VIN =0.7V 0.10 N-ch, VDS = 0.5V VIN =1.0V 0.85 CMOS, P-ch, VDS=2.1V VIN =6.0V VIN =1.0V 1.0 3.0 5. 0 6.0 7.0 -
CONDITIONS
TYP. VDF VDF x 0.05 0.7 0.8 0.9 1.0 1.1 0.80 2.70 -7.5 2.2 7.7 10.1 11.5 13.0 -10.0 100 -
MAX. VDF x 1.02 VDF x 0.08 2.3 2.7 3.0 3.2 3.6 6.0 10.0 -1.5 -2.0 0.2
UNITS V V
CIRCUITS 1 1
A
2
V
1 3 4
IOUT Output Current (Standard Voltage) N-ch, VDS = 0.5V
VIN =2.0V VIN =3.0V VIN =4.0V VIN =5.0V CMOS, P-ch, VDS=2.1V VIN =8.0V
mA 3
4 ppm/ ms 5
Temperature Characteristics Delay Time
(VDR VOUT inversion)
VDF Topr VDF tDLY
-40
Topr
85
NOTE : VDF (T) : Setting detect voltage Release Voltage : VDR = VDF + VHYS
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XC61G Series
OPERATIONAL EXPLANATION
CMOS output
When input voltage (VIN) rises above detect voltage (VDF), output voltage (VOUT) will be equal to VIN. ( A condition of high impedance exists with N-ch open drain output configurations. ) When input voltage (VIN) falls below detect voltage (VDF), output voltage (VOUT) will be equal to the ground voltage (VSS) level. When input voltage (VIN) falls to a level below that of the minimum operating voltage (VMIN), output will become unstable. In this condition, VIN will equal the pulled-up output ( should output be pulled-up.) When input voltage (VIN) rises above the ground voltage (VSS) level, output will be unstable at levels below the minimum operating voltage (VMIN). Between the VMIN and detect release voltage (VDR) levels, the ground voltage (VSS) level will be maintained. When input voltage (VIN) rises above detect release voltage (VDR), output voltage (VOUT) will be equal to VIN. ( A condition of high impedance exists with N-ch open drain output configurations. ) The difference between VDR and VDF represents the hysteresis range.
Timing Chart
106
XC61G
Series
NOTES ON USE
1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent damage to the device. 2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. ( refer to the Oscillation Description (1) below ) 3. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch output configurations, oscillation may occur as a result of through current at the time of voltage release even if load current (IOUT) does not exist. ( refer to the Oscillation Description (2) below ) 4. With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's supply current flowing through the VIN pin. 5. In order to stabilise the IC's operations, please ensure that VIN pin's input frequency's rise and fall times are more than several sec / V. 6. Please use N-ch open drains configuration, when a resistor RIN is connected between the VIN pin and power source. In such cases, please ensure that RIN is less than 10k and that C is more than 0.1F.
Oscillation Description
(1) Output current oscillation with the CMOS output configuration When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load current (IOUT) will flow at RL. Because a voltage drop ( RIN x IOUT) is produced at the RIN resistor, located between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the voltage level at the VIN pin will rise and release operations will begin over again. Oscillation may occur with this " release - detect - release " repetition. Further, this condition will also appear via means of a similar mechanism during detect operations. (2) Oscillation as a result of through current Since the XC61G series are CMOS IC S, through current will flow when the IC's internal circuit switching operates ( during release and detect operations ). Consequently, oscillation is liable to occur as a result of drops in voltage at the through current's resistor (RIN) during release voltage operations. ( refer to Figure 3 ) Since hysteresis exists during detect operations, oscillation is unlikely to occur.
107
XC61G Series
TEST CIRCUITS
108
XC61G
Series
TYPICAL PERFORMANCE CHARACTERISTICS
Low Voltage
109
XC61G Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Low Voltage (Continued)
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XC61G
Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Standard Voltage
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XC61G Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Standard Voltage (Continued)
112
XC61G
Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Standard Voltage (Continued)
113
XC61G Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Standard Voltage (Continued)
114

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